1. Field of the Invention
The present invention relates to a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an electromagnetic (EM) simulation, which analyzes and compensates a performance degradation region of the RFIC by using the EM simulation.
2. Description of the Related Art
In general, an RFIC is referred to as a circuit in which an RF circuit is implemented on one semiconductor chip using active and passive elements. The RFIC mainly includes an amplifier, a transmitter/receiver, a synthesizer and so on.
Such an RFIC operates in a several GHz band. Therefore, to predict the characteristic of the RFIC, an analysis on interference depending on the layout of the respective elements is essential. To perform fast analysis, a layout simulator is used.
Recently, the development speed of wireless communication systems gradually increases, and the high integration of wireless communication parts is realized. Therefore, there is a demand for a method for carrying out a fast and accurate layout simulation on more complex circuits and a method for compensating performance degradation.
Hereinafter, a conventional method for designing an RFIC will be described with accompanying drawings.
FIG. 1 is a flow chart sequentially showing a conventional method for designing an RFIC.
First, as shown in FIG. 1, the design specifications of an RFIC are extracted in accordance with characteristics of the RFIC (step S10).
After the design specifications are extracted in step S10, a semiconductor process is set in consideration of the performance and manufacturing cost of the RFIC, a circuit is designed using characteristics of active and passive elements required when the RFIC is designed, and a circuit simulation of the designed circuit is carried out using a circuit simulation tool (step S20).
When the circuit design is completed, a layout is carried out on the basis of the designed circuit. In the layout process, the size of the RFIC and the distance and disposition of pads required for measurement are determined. Further, the active and passive elements are respectively disposed and connected to each other through a transmission line (step S30).
When the layout process is completed, a layout parameter extraction process is performed. In the layout parameter extraction process, a DRC (Design Rule Checker) for checking whether the layout satisfies a process condition of the RFIC or not, a LVS (Layout Versus Schematic) for checking whether the wiring connection of the layout coincides with a circuit diagram or not, and a parasitic parameter are extracted to carry out RCX, in which a circuit simulation is carried out, thereby analyzing a layout characteristic (step S40).
The layout parameters extracted through step S40 are applied to the circuit simulation tool so as to carry out a circuit simulation (step S50).
Then, it is judged whether or not the results of the circuit simulation carried out in step S50 satisfy the design specifications of the RFIC (step S60).
When it is not judged at step S60 that the results of the circuit simulation satisfy the design specifications of the RFIC, the process is fed back to step S20. Then, the process is repeated from the step for performing the circuit design.
Otherwise, when it is judged at step S60 that the results of the circuit simulation satisfy the design specifications of the RFIC, a process of manufacturing the RFIC is performed (step S70).
In the conventional method, however, the results of the circuit simulation may differ from the measured results, because of an effect of interference depending on the layout of elements. In this case, the circuit should be re-designed, so that the circuit design time increases.
Further, when the simulation using the simulation tool is carried out on the RFIC which gradually becomes complex, a long time is required. Therefore, the circuit analysis process takes a long time.